1 july 12, 2013 fn3025.5 radiation hardened, low noise quad operational amplifiers hs-5104arh, hs-5104aeh the hs-5104arh, hs-5104aeh are radiation hardened, monolithic quad operational amplifiers that provide highly reliable performance in harsh radiation environments. excellent noise characteristics coupled with a unique array of dynamic specifications make these amplifiers well-suited for a variety of satellite system applications. dielectrically isolated, bipolar processing makes these devices immune to single event latch-up. the hs-5104arh, hs-5104aeh show almost no change in offset voltage after exposure to 100k rad(si) gamma radiation, with only a minor increase in current. complementing these specifications is a post radiation open loop gain in excess of 40k. these quad operational amplifiers are available in an industry standard pinout, allowing for immediate interchangeability with most other quad operational amplifiers. features ? electrically screened to smd # 5962-95690 ? qml qualified per mil-prf-38535 requirements ?radiation environment - high dose rate (50-300rad(si)/s). . . . . . . . . . . 100krad(si) - low dose rate (0.01rad(si)/s) . . . . . . . . . . . . . . .50krad(si) ? no latch-up, dielectrically isolated device islands ?low noise - at 1khz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3nv/ hz (typ) - at 1khz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.6pa/ hz (typ) ? low offset voltage . . . . . . . . . . . . . . . . . . . . . . . . . 3.0mv (max) ? high slew rate . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.0v/s (typ) ? gain bandwidth product . . . . . . . . . . . . . . . . . . . .8.0mhz (typ) applications ? high q, active filters ? voltage regulators ?integrators ? signal generators ?voltage references ?space environment ordering information ordering/smd number internal mkt. number (note 1 ) temp. range (c) part marking package (rohs compliant) (note 2) pkg. dwg. # 5962r9569001vxc hs9-5104arh-q -55 to +125 q 5962r95 69001vxc 14 ld flatpack k14.a 5962r9569002vxc hs9-5104aeh-q -55 to +125 q 5962r95 69002vxc 14 ld flatpack k14.a 5962r9569001vcc hs1-5104arh-q -55 to +125 q 5962r95 69001vcc 14 ld sbdip d14.3 5962r9569002vcc hs1-5104aeh-q -55 to +125 q 5962r95 69002vcc 14 ld sbdip d14.3 5962r9569001v9a hs0-5104arh-q -55 to +125 die 5962r9569002v9a hs0-5104aeh-q -55 to +125 die hs1-5104arh/proto hs1-5104arh/proto -55 to +125 hs1-5104arh/proto 14 ld sbdip d14.3 hs0-5104arh/sample hs0-5104arh/sample -55 to +125 die hs9-5104arh/proto hs9-5104arh/proto -55 to +125 hs9-5104arh/proto 14 ld flatpack k14.a 1. specifications for rad hard qml devices are controlled by the defense logistics agency land and maritime (dla). the smd numbe rs listed in the?ordering information? table must be used when ordering. 2. these intersil pb-free hermetic packaged products employ 100% au plate - e4 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations. caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas llc 2002, 2013. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
hs-5104arh, hs-5104aeh 2 fn3025.5 july 12, 2013 pin configuration hs1-5104arh, hs1-5104aeh (14 ld sbdip) top view hs9-5104arh, hs9-5104aeh (14 ld flatpack) top view irradiation circuit notes: 3. +v = 15v 4. -v = -15v 5. group e sample size = 4 die per wafer burn in circuit notes: 6. r1 = r2 = r3 = r4 = 1mw, 5%, 1/4w (min) 7. c1 = c2 = 0.01f/socket (min) or 0.1f/row (min) 8. d1 = d2 = in4002 or equivalent/board 9. |(v+) - (v-)| = 31v 1v 1 2 3 4 5 6 7 14 13 12 11 10 9 8 v+ out 1 -in1 +in1 +in2 -in2 out 2 v- out 3 out 4 -in3 +in3 +in4 -in4 v+ out 1 -in1 +in1 +in2 -in2 out 2 v- out 3 out 4 -in3 +in3 +in4 -in4 14 13 12 11 10 9 8 2 3 4 5 6 7 1 + +15v -15v (one of four) - 1 2 3 4 5 6 7 14 13 12 11 10 9 8 1 4 2 3 c1 d1 +v c2 d2 -v r2 r1 r3 r4 + - + - + - + -
hs-5104arh, hs-5104aeh 3 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn3025.5 july 12, 2013 for additional products, see www.intersil.com/en/products.html die characteristics die dimensions: 95 mils x 99 mils x 19 mils 1 mils (2420m x 2530m x 483m 25.4m) interface materials: glassivation: type: nitride (si3n4) over silox (sio2, 5% phos.) silox thickness: 12k ? 2k ? nitride thickness: 3.5k ? 1.5k ? top metallization: type: al, 1% cu thickness: 16k ? 2k ? substrate: bipolar dielectric isolation backside finish: silicon assembly related information: substrate potential (powered up): unbiased additional information: worst case current density: <2.0 x 10 5 a/cm 2 transistor count: 175 metallization mask layout hs-5104arh, hs-5104aeh +in2 v+ +in1 -in1 out1 out4 -in4 -in3 out3 out2 -in2 +in4 v- +in3
hs-5104arh, hs-5104aeh 4 fn3025.5 july 12, 2013 ceramic metal seal fl atpack packages (flatpack) notes: 1. index area: a notch or a pin one id entification mark shall be located adjacent to pin one and shall be located within the shaded area shown. the manufacturer?s identific ation shall not be used as a pin one identification mark. alternately, a tab (dimension k) may be used to identify pin one. 2. if a pin one identification mark is used in addition to a tab, the limits of dimension k do not apply. 3. this dimension allows for off-c enter lid, meniscus, and glass over- run. 4. dimensions b1 and c1 apply to lead base metal only. dimension m applies to lead plating and finish th ickness. the maximum limits of lead dimensions b and c or m s hall be measured at the centroid of the finished lead surfaces, when sol der dip or tin plate lead finish is applied. 5. n is the maximum number of terminal positions. 6. measure dimension s1 at all four corners. 7. for bottom-brazed lead packages, no organic or polymeric materi- als shall be molded to the bottom of the package to cover the leads. 8. dimension q shall be measured at the point of exit (beyond the me- niscus) of the lead from the bo dy. dimension q minimum shall be reduced by 0.0015 inch (0.038mm) maximum when solder dip lead finish is applied. 9. dimensioning and tolerancing per ansi y14.5m - 1982. 10. controlling dimension: inch. -d- -c- 0.004 h a - b m d s s -a- -b- 0.036 h a - b m d s s e e a q l d a e1 seating and l e2 e3 e3 base plane -h- b c s1 m c1 b1 (c) (b) section a-a base lead finish metal pin no. 1 id area a m k14.a mil-std-1835 cdfp3-f14 (f-2a, configuration b) 14 lead ceramic metal seal flatpack package symbol inches millimeters notes min max min max a 0.045 0.115 1.14 2.92 - b 0.015 0.022 0.38 0.56 - b1 0.015 0.019 0.38 0.48 - c 0.004 0.009 0.10 0.23 - c1 0.004 0.006 0.10 0.15 - d - 0.390 - 9.91 3 e 0.235 0.260 5.97 6.60 - e1 -0.290-7.11 3 e2 0.125 - 3.18 - - e3 0.030 - 0.76 - 7 e 0.050 bsc 1.27 bsc - k 0.008 0.015 0.20 0.38 2 l 0.270 0.370 6.86 9.40 - q 0.026 0.045 0.66 1.14 8 s1 0.005 - 0.13 - 6 m - 0.0015 - 0.04 - n14 14- rev. 0 5/18/94
hs-5104arh, hs-5104aeh 5 fn3025.5 july 12, 2013 ceramic dual-in-line me tal seal packages (sbdip) notes: 1. index area: a notch or a pin one id entification mark shall be located adjacent to pin one and shall be located within the shaded area shown. the manufacturer?s identific ation shall not be used as a pin one identification mark. 2. the maximum limits of lead di mensions b and c or m shall be mea- sured at the centroid of the fini shed lead surfaces, when solder dip or tin plate lead finish is applied. 3. dimensions b1 and c1 apply to lead base metal only. dimension m applies to lead plating and finish thickness. 4. corner leads (1, n, n/2, and n/2+1) may be configured with a par- tial lead paddle. for this configur ation dimension b3 replaces di- mension b2. 5. dimension q shall be measured from the seating plane to the base plane. 6. measure dimension s1 at all four corners. 7. measure dimension s2 from the top of the ceramic body to the near- est metallization or lead. 8. n is the maximum number of terminal positions. 9. braze fillets shall be concave. 10. dimensioning and tolerancing per ansi y14.5m - 1982. 11. controlling dimension: inch. bbb c a - b s c q l a seating base d plane plane s s -d- -a- -c- e a -b- aaa ca - b m d s s ccc ca - b m d s s d e s1 b2 b a e m c1 b1 (c) (b) section a-a base lead finish metal e a/2 s2 m a d14.3 mil-std-1835 cdip2-t14 (d-1, configuration c) 14 lead ceramic dual-in-line metal seal package symbol inches millimeters notes min max min max a - 0.200 - 5.08 - b 0.014 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 d - 0.785 - 19.94 - e 0.220 0.310 5.59 7.87 - e 0.100 bsc 2.54 bsc - ea 0.300 bsc 7.62 bsc - ea/2 0.150 bsc 3.81 bsc - l 0.125 0.200 3.18 5.08 - q 0.015 0.060 0.38 1.52 5 s1 0.005 - 0.13 - 6 s2 0.005 - 0.13 - 7 90 o 105 o 90 o 105 o - aaa - 0.015 - 0.38 - bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - m - 0.0015 - 0.038 2 n14 148 rev. 0 4/94
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